The Internet is fundamentally changing the face of networking. Network traffic grows greater and greater each year. Network providers need optical transport solutions that provide high volume channel count, capacity per channel, optical link distance, and sufficient physical space in order to carry the increased traffic.
Current state of the art networks provide 10 Gb/s (Gigabit per second) capacity per optical channel. However, this is not expected to provide sufficient bandwidth to carry projected traffic on the Internet. The next step is believed to be an increase to a 40 Gb/s per channel high-speed fiber-optic communication system.
In high-speed fiber-optic communication systems, Awhere digital data is transmitted in an analog input data signal, digital receiver performance is determined by the ability to detect the digital data in the analog input data signal and recover the clock signal contained therein. An eye diagram, a graphical representation of a signal with fluctuations in the amplitude on the vertical axis and time on the horizontal axis, provides a convenient way to understand the impact of amplitude fluctuations on the performance of a digital receiver. A typical eye diagram of an ideal analog input data signal is a flat curve (FIG. 1). Amplitude jitter strongly impacts the eye diagram of the analog input data signal, and a large amount of jitter changes the shape of the eye diagram significantly away from the ideal flat curve, making it difficult to recover the digital data contained in the analog input data signal (FIG. 2).
It is, of course, necessary to recover the digital data contained in the analog input data signal for the digital receiver to be useful. One prior art circuit for recovering digital data has employed a master-slave D-type flip-flop, which receives the analog input data signal and generates a digital zero or digital one at its output terminal, thereby recovering the digital data (FIG. 3). Such a prior art circuit recovers the data by sampling the analog input data signal at predetermined intervals. The phase difference between the master-slave D-type flip-flop clock signal and the input data signal determines the instant when the sampling occurs. Typically, this occurs in “mid-bit,” that is, in the middle of the time period allowed for the transmission of the bit.
Known clock recovery circuits based on a binary type or Alexander type phase detector are considered to be self-aligned, i.e., the analog input data signal is sampled in the mid-bit position. The input swing or vertical eye opening at the sampling instant has a significant impact on the ability of the master-slave D-type flip-flop to recover digital data. If an ideal analog data signal is sampled in mid-bit position with the clock phase, the vertical eye opening is maximized, leading to optimized data recovery (FIG. 4). However, when the analog input data signal possesses significant amplitude jitter, mid-bit sampling frequently does not occur at the moment of maximized vertical eye opening, thus resulting in a degraded sample and faulty recognition of the digital data (FIG. 5). In such an instance, the moment of sampling may not be optimal for accurate recovery of the digital data.